Different architectures of processor devices are well known in the art. Matrix processors have advantages related to high parallelism, structure uniformity and possible scalability. Typically, conventional matrix processors consist of a plurality of electronic components, only, each designed to perform a different kind of operation (i.e., adder, multiplier, etc.) These components may be programmable arithmetical and logical units which utilize shared, usually concurrently accessible code and data memory resources with a small number of per unit fast registers and cache memories. Each such component can perform only one or a limited number of logical operations, which limits the applications which each such processor can implement. In the case of programmable devices, using software brings more flexibility. However, such devices are limited by speed (rate of processing). In addition, the use of shared resources may lead to starvation of processing units and decrease the rate of processing.
In order to increase the rate of processing, processors using optical components have been proposed. However, such devices are typically limited to one multiplication per time clock. While the rate of operation and parallelism could be high by using optics, operation of these devices is very specific. One such processor performs fast multiplication of a fixed size input vector on a slowly changing fixed size matrix, thus obtaining a fixed size resulting vector. The majority of existing embodiments of “optical” processors have the same (or similar) drawbacks: non-flexible processing data structure and very limited (unvarying or slowly varying) reprogramming capabilities.
Due to the structure of conventional optical processors with vector matrix multiplication architecture (one fixed length vector is multiplied on one fixed size matrix (which can be slowly updated)), these devices cannot perform the full range of logical operations or rotational shift of long strings with different lengths, permutation of bits in a string, correlation between different strings, etc.
Accordingly, there is a long felt need for a relatively simple device for performing matrix processing at high speeds and low power consumption that permits performance of correlation and logical functions on strings of data.